Static Timing Analysis (“STA”) has been used to calculate delays in synchronous digital systems and validate conformance to timing specifications. Enhancements have been added to STA. For example, enhancements have been added to the application of statistical methods to handle random process variations.
A basic assumption underlying STA algorithms is that a library of logic cells may be pre-characterized using, for example, a Simulation Program with Integrated Circuit Emphasis simulator (“SPICE simulator”) to build cell models, and that these models may be used for each instance of a specific cell.
However, in deep sub-micron processes employing physical strain to enhance the mobility of Field-Effect Transistors (“FETs”), interaction between adjacent cell instances may significantly alter the carrier mobility of the same transistor in different instances of the same cell. This effect is illustrated in FIG. 1. Here, instance I1 and I2 of the same 2-in NOR have different MOSFET strain due to their differing interactions with neighbor cells; therefore, the 2-in NORs have different electrical characteristics in spite of having identical layouts. As a result, the cell-based modeling algorithm may break down. There are numerous approaches to alleviating this problem. Three approaches are described below.
A first approach is to simulate each cell in a variety of layouts and build a statistical model. A problem with this approach is that the individual instances have systematic variations, instead of random variations. Applying a statistical model to a problem with knowable systematic variation is overly pessimistic, resulting in larger cycle times or unnecessary padding of short paths.
A second approach is to simulate each cell in the minimum and maximum strain condition and build corner models. A problem with this approach is similar to the first approach described above: the strain of each instance is knowable from the layout, so applying a worst-case model is overly pessimistic, resulting in larger cycle times or unnecessary padding of short paths.
A third approach is to impose rigid design rules that equalize the strain on each FET so that a single timing model predicts the delay accurately for every instance. A problem with this approach is that it results in fixed FET size (gate array style) layouts resulting in suboptimal performance of the cell library compared to the less-constrained standard-cell style layout. This approach is illustrated in FIG. 2. In FIG. 2, assume that the transistors are the same width. Here, instance I1 and I2 of the same 2-in NOR have the same MOSFET strain and electrical characteristics due to their identical interactions with neighbor cells.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.